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Message
From: "Robert Cragie" <rcc@j...>
Date: Wed, 17 Sep 2003 11:11:47 +0100
Subject: RE: [openrisc] accessing JTAG lines of Xilinx Virtex-II
I agree with Tomas, the JTAG interface for the OR1200 needs to be on a
separate interface - standard I/O pins will be OK. Even if you could include
it on the scan chain of the Xilinx device, the existing software and
interface for the debugger will not work as it is, as I'm sure it only
expects one device (i.e. the OR1200 itself) on its scan chain.
Robert Cragie, Design Engineer
_______________________________________________________________
Jennic Ltd, Furnival Street, Sheffield, S1 4QT, UK
http://www.jennic.com Tel: +44 (0) 114 281 2655
_______________________________________________________________
> -----Original Message-----
> From: owner-openrisc@o...
> [mailto:owner-openrisc@o...]On Behalf Of Tomas Jonsson
> Sent: 17 September 2003 09:29
> To: openrisc@o...
> Subject: SV: [openrisc] accessing JTAG lines of Xilinx Virtex-II
>
>
>
> For Spartan-II I these pins are reserved. You have to use another I/O pins
> than the XILINX JTAG interface. That means for example you have
> to use some
> general I/O pins on the board. These I/O pins might be connected
> to a cable
> connected to the PC parallel port. After that you can use the
> JTAG facility
> (or1k/jtag).
>
> I think you cannot bypass the xilinx BS but you can extend by
> your own jtag
> chains (limited). If you do that you also have to design a new test
> interface which handles these chains. Correct me if I am wrong.
>
> Best regards,
> Tomas
>
> -----Ursprungligt meddelande-----
> Fran: owner-openrisc@o...
> [mailto:owner-openrisc@o...]For Dries Driessens
> Skickat: den 17 september 2003 09:55
> Till: openrisc@o...
> Amne: Re: [openrisc] accessing JTAG lines of Xilinx Virtex-II
>
>
> I already considered that option, but unfortunately, I don't have an
> additional JTAG interface on my FPGA board. Therefor I would like to use
> the 'download' JTAG interface.
>
> I have read in Xilinx Answer 1356 and 4641 that if boundary scan isn't
> enabled (bscan macro is not instantiated) that TCK, TMS, TDI, TDO can be
> used as I/O pins.
>
> So is there anybody that has been able to accomplish this? How
> did he do it?
>
> Best regards,
> Dries
>
> Michael Unneback wrote:
>
> > Hi Dries,
> >
> > there are no stupid questions.
> >
> > Xilinx FPGA's have dedicated pins for JTAG. These pins can be used for
> > test purposes in production
> > of your PCB, checking that the correct device is present for example,
> > and for configuration of the
> > FPGA.
> >
> > If you are using the OR1200 you most likely have a JTAG debug port in
> > your design. These JTAG
> > signals are ordinary IO signals. Nothing special about them except for
> > the names perhaps. TCK, TMS
> > and so on might be reserved words, if so just name your debug signals
> > something like dbg_tms. These
> > signals can be placed in any IO block.
> >
> > regards
> > /Michael Unneback
> > HDC
> >
> > Dries Driessens wrote:
> >
> >> Hello everybody,
> >>
> >> maybe a stupid question, but I just can't figure this one out.
> >>
> >> How do you access the JTAG lines (TCK, TMS, TDI and TDO) of a Xilinx
> >> FPGA?
> >>
> >> I've read a dozen "xilinx answer records" and Application Notes, but I
> >> can't add them.
> >>
> >> I tried:
> >> * use the JTAG locations (B3,C4,...) in the constraint file, but
> >> JTAG-pins are already locked.
> >> * use the JTAG names(TCK, TMS,...) in the constraint file, but
> >> JTAG-names can't be used.
> >> * use the JTAG names as port names, but ISE doesn't recognize them as
> >> JTAG pins and just places them randomly (checked with FPGA editor)
> >> * change the placed pins to the JTAG locations, but FPGA editor
> >> doesn't want to place pins to locked pins.
> >> * using JTAG pin cells (component TDI, etc) doesn't work for Virtex,
> >> only for older 4000,5000 and Spartan FPGA families.
> >>
> >> Do I have to add/change lines to the constraint file? Or just to the
> >> HDL-source files?
> >>
> >> Thank you for sharing your experience!
> >>
> >> Best regards,
> >> Dries
> >>
> >>
> >>
> >
> >
> >
> >
> >
>
>
>
>
>
>
>
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