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Message
From: Daniel Wiklund <danwi@i...>
Date: Wed, 17 Sep 2003 10:26:21 +0200
Subject: Re: [openrisc] accessing JTAG lines of Xilinx Virtex-II
On Wed, 17 Sep 2003 09:55:26 +0200
Dries Driessens <ddr@d...> wrote:
> I already considered that option, but unfortunately, I don't have an
> additional JTAG interface on my FPGA board. Therefor I would like to
> use the 'download' JTAG interface.
>
> I have read in Xilinx Answer 1356 and 4641 that if boundary scan isn't
> enabled (bscan macro is not instantiated) that TCK, TMS, TDI, TDO can
> be used as I/O pins.
>
> So is there anybody that has been able to accomplish this? How did he
> do it?
Answers 1356 and 4641 are only valid for the XC4000 and XC5200
families. Newer FPGAs (e.g. Spartan3) have dedicated interfaces for JTAG
that cannot be used for anything else than the fixed JTAG functions. I
presume that you have a more recent FPGA on your board which makes it
impossible to use the JTAG interface for "user JTAG".
But if you have four general purpose IO pins free and available to the
outside you can use them for the debug JTAG. There is nothing fancy
about the JTAG signalling that would prevent this solution.
// Daniel
----
Daniel Wiklund, MScEE, Lic Eng
Computer Engineering, ISY
Linköping University
581 83 Linköping
Sweden
danwi@i...
http://www.da.isy.liu.se/~danwi/
----
Inter spem curamque, timores inter et iras
omnem crede diem tibi diluxisse supremem:
grata superveniet quae non sperabitur hora.
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