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Message
From: Michael Unneback <michael@h...>
Date: Wed, 17 Sep 2003 09:30:38 +0200
Subject: Re: [openrisc] accessing JTAG lines of Xilinx Virtex-II
Hi Dries,
there are no stupid questions.
Xilinx FPGA's have dedicated pins for JTAG. These pins can be used for
test purposes in production
of your PCB, checking that the correct device is present for example,
and for configuration of the
FPGA.
If you are using the OR1200 you most likely have a JTAG debug port in
your design. These JTAG
signals are ordinary IO signals. Nothing special about them except for
the names perhaps. TCK, TMS
and so on might be reserved words, if so just name your debug signals
something like dbg_tms. These
signals can be placed in any IO block.
regards
/Michael Unneback
HDC
Dries Driessens wrote:
> Hello everybody,
>
> maybe a stupid question, but I just can't figure this one out.
>
> How do you access the JTAG lines (TCK, TMS, TDI and TDO) of a Xilinx
> FPGA?
>
> I've read a dozen "xilinx answer records" and Application Notes, but I
> can't add them.
>
> I tried:
> * use the JTAG locations (B3,C4,...) in the constraint file, but
> JTAG-pins are already locked.
> * use the JTAG names(TCK, TMS,...) in the constraint file, but
> JTAG-names can't be used.
> * use the JTAG names as port names, but ISE doesn't recognize them as
> JTAG pins and just places them randomly (checked with FPGA editor)
> * change the placed pins to the JTAG locations, but FPGA editor
> doesn't want to place pins to locked pins.
> * using JTAG pin cells (component TDI, etc) doesn't work for Virtex,
> only for older 4000,5000 and Spartan FPGA families.
>
> Do I have to add/change lines to the constraint file? Or just to the
> HDL-source files?
>
> Thank you for sharing your experience!
>
> Best regards,
> Dries
>
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