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Message
From: ddr@d...
Date: Sat, 13 Sep 2003 01:48:45 +0200
Subject: Re: [openrisc] UART16550 problems
My problem was the 'new' 8-bit mode of the UART16550 which didn't
work with the OpenRISC. Simply disabling it solved the problem
I patched the OpenRisc CVS-repository...
Many thanks to all contributors
Dries
----- Original Message -----
From: "Damjan Lampret" <lampret@o... >
To: <openrisc@o... >
Date: Tue, 9 Sep 2003 16:24:55 +0200
Subject: Re: [openrisc] UART16550 problems
>
>
> Hi Dries,
>
> since you already resolved the problem I will not reply. If I
> understand you
> correctly in your private email, you will let know others what the
> problem
> was. Thanks.
>
> regards,
> Damjan
>
> ----- Original Message -----
> From: "Dries Driessens" <ddr@d... >
> To: <openrisc@o... >
> Sent: Tuesday, September 09, 2003 2:20 PM
> Subject: Re: [openrisc] UART16550 problems
>
>
> > Hi Damjan,
> >
> > thanks to the advice of some to read/write my registers in a
> different
> > way here are the faulty readings that I get.
> > (Always keep in mind that I use original Verilog code
> extracted from CVS
> > last week...)
> >
> > here comes the register-readout after I'd set the enable
> divisor latch
> > bit bit (REG8(0x90000003)|=0x80) and written the divisor latch
> > (REG8(0x90000000)=0x20 and REG8(0x90000001)=0x00)
> >
> > * REG8(0x9000000) : 0x00
> > * REG8(0x9000001) : 0x00
> > * REG8(0x9000002) : 0x00
> > * REG8(0x9000003) : 0x83
> > * REG8(0x9000004) : 0x00
> > * REG8(0x9000005) : 0x00
> > * REG8(0x9000006) : 0x00
> > * REG8(0x9000007) : 0x03
> > ...and so on (of course)
> >
> > * REG32(0x9000000) : 0x20
> > * REG32(0x9000004) : 0x00
> > * REG32(0x9000008) : 0x20
> > * REG32(0x900000C) : 0x00
> > ...and so on
> >
> > I find it quite strange that the data isn't the same when I
> read bytes
> > or when I read long words...
> > The reason why I find it strange is because the uart is in 8
> bit mode
> > (as in the original XESS ORP code), so the UART shouldn't be
> able to see
> > the difference between long word readings or byte readings...
> > (line 239 of uart_top.v: ".wb_sel_i(4'b0)," )
> >
> > very strange! or not?
> > or maybe my problem is c-compiler related?
> >
> > SOLUTION:
> > anyway, I think I'm going to try 2 things:
> > - change 3 bit address bus (8-bit) into 5-bit, so I can
> hopefully read
> > all the registers with REG32
> > - try 32-bit mode
> >
> > Many thanks to all contributing people!
> > Best regards,
> >
> > Dries
> >
> > Damjan Lampret wrote:
> >
> > > Hi Dries,
> > >
> > > Strange. I can tell you it works for me. On the board,
> not just in
> > > simulation. It seems there is something wrong with your
> implementation.
> > >
> > > Maybe you can do the following. Try to run a simple
> simulation of the
> > > netlist writing into one of the UART registers (as
> opposed to RTL
> simulation
> > > that works). If also netlist simulation works, then it
> must be something
> > > wrong with your P&R tools.
> > >
> > > regards,
> > > Damjan
> > >
> >
> >
> >
>
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