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    Navigation: All forums > Openrisc > Message List > Message Post

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    From: "Damjan Lampret" <lampret@o...>
    Date: Tue, 9 Sep 2003 19:03:21 +0200
    Subject: Re: [openrisc] RTL tests
    Top

    When I say verilog simulator, I mean run_rtl_regression script is for
    Cadence NCsim (or if you prefer ncverilog).
    
    Both types of simulations generate log files that naturally go into
    orp_soc/sim/log directory. There are differences between log files generated
    by verilog simulation and with or1ksim. They are prefixed differently, one
    with 'i' and the other I can't remember right now. There is also number
    involved, for example i1-except-nocache-executed.log: verilog simulation,
    iteration 1, except test case with no caches enabled in SW, executed log.
    Executed log shows list of all instructions executed, their PC, SR and state
    of all general purpose registers. Same executed log is also produced by
    or1ksim, so it is natural to compare the two executed logs and see if
    or1ksim and verilog simulation match down to every instruction executed.
    Maybe I also explain iterations - basically same test cases are rerun under
    differently configured test bench and/or RTL - for example memory can be
    slower or faster, processor can be clocked differently etc.
    
    regards,
    Damjan
    
    ----- Original Message ----- 
    From: "Brian Korsedal" <BKorsedal@b...>
    To: <openrisc@o...>; <openrisc@o...>
    Sent: Tuesday, September 09, 2003 6:39 PM
    Subject: RE: [openrisc] RTL tests
    
    
    > I'd rather reuse or extend something existing so I'll look into this.  It
    > sounds like this will do what I would like to see.
    >
    > Thanks,
    >
    > Brian
    >
    >
    > -----Original Message-----
    > From: Damjan Lampret [mailto:lampret@o...]
    > Sent: Tue 9/9/2003 7:29 AM
    > To: openrisc@o...
    > Cc:
    > Subject: Re: [openrisc] RTL tests
    > Hi,
    >
    > if you download orp_soc, you can run SW test cases found in orp_soc/sw
    > either with command orp_soc/sim/bin/run_rtl_regression to run it on
    verilog
    > simulator, or with orp_soc/sim/bin/run_sw for running test cases on
    or1ksim.
    >
    > But I'm definately all for it to expand the test cases, or even create a
    new
    > environment if you have created an environment already.
    >
    > regards,
    > Damjan
    >
    > ----- Original Message ----- 
    > From: "Brian Korsedal" <BKorsedal@b...>
    > To: <openrisc@o...>; <openrisc@o...>;
    > <openrisc@o...>
    > Sent: Tuesday, September 09, 2003 4:01 AM
    > Subject: [openrisc] RTL tests
    >
    >
    > > Hi,
    > >
    > > I was wondering if there has been any work to run software/hardware
    co-sim
    > > for the or1k.  I did some work where we did the hardware if verilog and
    > did
    > > an extensive verification enviroment in C.  We ran it all on a verilog
    > > simulator.
    > >
    > > I was thinking that it would be nice to use the actual RTL instead of
    the
    > > or1k sim.  It would probably be a lot LOT slower but it would still be
    > > really nice.  Maybe get most of the work done with the or1k sim and then
    > run
    > > the RTL simulator to be sure it all works.
    > >
    > > Anyway, has there been any work done twoards this?  If not, what
    simulator
    > > should it be written for?  I was thinking Icarus Verilog because it's
    > free.
    > >
    > >
    > > -Brian
    > >
    > >
    > > -----Original Message-----
    > > From: owner-openrisc@o... on behalf of Brian Korsedal
    > > Sent: Mon 9/8/2003 1:43 PM
    > > To: openrisc@o...; openrisc@o...
    > > Cc:
    > > Subject: RE: [openrisc] Where to get source files?
    > >
    > >
    > > I'll try to compile and set the one from uclinux.  If I can do it and
    > > everything works good, I'll post the results here.  It might take me a
    few
    > > days or a week or so.
    > >
    > > -Brian
    > >
    > > -----Original Message-----
    > > From: Damjan Lampret [mailto:lampret@o...]
    > > Sent: Mon 9/8/2003 1:26 PM
    > > To: openrisc@o...
    > > Cc:
    > > Subject: Re: [openrisc] Where to get source files?
    > > I don't know which one is better, but I can tell you that the one from
    > > opencores cvs runs for sure. See this:
    > > http://www.opencores.org/cores/or1k/ats/or32-uclinux/or1ksim_uclinux.txt
    > >
    > > You can also try from uclinux.org, maybe yoiu can do a diff a report if
    > > there are differences. Anyway I'm all for it to remove the one from
    > > opencores cvs if they are the same (so that people will not get
    confused).
    > > The main reason for having a copy in opencores cvs is during development
    > > when changes are often and it is difficult to send patches to official
    > site
    > > all the time (maintainers get tired of you ;-)
    > >
    > > regards,
    > > Damjan
    > >
    > > ----- Original Message ----- 
    > > From: "Brian Korsedal" <BKorsedal@b...>
    > > To: <openrisc@o...>; <openrisc@o...>
    > > Sent: Monday, September 08, 2003 10:08 PM
    > > Subject: RE: [openrisc] Where to get source files?
    > >
    > >
    > > > I was just looking over at the uClinux.org
    > > > (http://www.uclinux.org/pub/uClinux/dist/)
    > > > site and they have 'OPENcores OR1000' support.  Which one is better,
    the
    > > > files from cvs@opencores or the ones from uclinux.org?  The files are
    > > dated
    > > > 22 May 2003 for uclinux.org.
    > > >
    > > > I think the uclinux.org release is the most recent stable source code.
    > > > Anyone know which one is better?
    > > >
    > > > -Brian
    > > >
    > > > -----Original Message-----
    > > > From: Damjan Lampret [mailto:lampret@o...]
    > > > Sent: Mon 9/8/2003 11:33 AM
    > > > To: openrisc@o...
    > > > Cc:
    > > > Subject: Re: [openrisc] Where to get source files?
    > > > Hi,
    > > >
    > > > some of the files where takene from official sites, modified and then
    > > > imported into the cvs (1.1.1.1). I don't remember which packages and
    > > amount
    > > > of their changes. In general those that are mainly 1.1.1.1 do not
    change
    > > > much from originals. The simplest way is to compare the original files
    > and
    > > > the one in opencores cvs.
    > > >
    > > > There is now also plan to move as much as possible of openrisc
    toolchain
    > > > into official sources trees of gcc, binutils (at GNU/FSF), same for
    > linux.
    > > > Something similar I think is already the case for eCos.
    > > >
    > > > regards,
    > > > Damjan
    > > >
    > > > ----- Original Message ----- 
    > > > From: "Brian Korsedal" <BKorsedal@b...>
    > > > To: <openrisc@o...>
    > > > Sent: Monday, September 08, 2003 8:23 PM
    > > > Subject: [openrisc] Where to get source files?
    > > >
    > > >
    > > > > Hi,
    > > > >
    > > > > I was looking around in the CVS directory and checking out the dates
    > and
    > > > > release numbers for some of the files.  It seems that some things,
    > like
    > > > > uclibc and newlib the files were very old and not modified (version
    > > > > 1.1.1.1).
    > > > >
    > > > > I was curious if these sources are different than those that can be
    > > found
    > > > at
    > > > > the website of the project.  Such as, will I find newer source code
    > from
    > > > the
    > > > > newlib project page?  If so, what changes need to be made for the
    > or1k?
    > > > Is
    > > > > it just compile and install options that have to be different or are
    > > there
    > > > > changes to the souce code.
    > > > >
    > > > > Thanks,
    > > > >
    > > > > Brian
    > > > >
    > > >
    > > > 
    > > >
    > > >
    > > >
    > >
    > > 
    > >
    > >
    > >
    >
    > 
    >
    >
    >
    
    
    
    

    ReferenceAuthor
    RE: [openrisc] RTL testsBrian Korsedal

     
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