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Message
From: Brian Korsedal <BKorsedal@b...>
Date: Sat, 30 Aug 2003 10:25:55 -0700
Subject: RE: [openrisc] Wishbone example and driver writing for uCLinux wishbone cores.
Thank you, this message clarifies many things for me. I work with
commercial companies and open source groups. The feedback I get from the
OSS community on newsgroups is usually better and faster than I get from the
pro's. Keep up the good help (except Cypress and Avnet, who give great
support).
-Brian
-----Original Message-----
From: owner-openrisc@o... on behalf of Robert Cragie
Sent: Fri 8/29/2003 1:26 AM
To: openrisc@o...
Cc:
Subject: RE: [openrisc] Wishbone example and driver writing for
uCLinux wishbone cores.
If you have a new device sitting on the wishbone bus and want to write a
device driver for it, I would recommend the book "Linux Device Drivers", by
Alessandro Rubini and Jonathan Corbet (ISBN 0-596-00008-1). There are also
plenty of resources on the Internet. Whilst there are no doubt many corners
which could be cut using uCLinux, it is advisable to write device drivers in
a compliant way for portability. In a nutshell, you write a driver
conforming to the Linux device driver interface specification and can then
either statically patch it into the kernel or load it dynamically using the
module manager. You then add a device node into the file system in the /dev
directory and access it through the usual open/close/read/write/ioctl calls.
I should add I am speaking from my PC linux experiences here, not uCLinux in
particular, so there may be differences.
If you want to access an existing device on the wishbone bus via an existing
device driver (e.g. the serial port), the device driver will already be
loaded either statically or dynamically, it will have a node in the file
system and you can access it through the usual open/close/read/write/ioctl
calls.
Note that the wishbone bus is transparent and all devices are at fixed
locations on it, unlike a 'plug-and-play' bus with configuration and
enumeration like PCI. So there is no 'library to output to the wishbone bus'
as a device on the bus is simply memory-mapped at a fixed location.
Robert Cragie, Design Engineer
_______________________________________________________________
Jennic Ltd, Furnival Street, Sheffield, S1 4QT, UK
http://www.jennic.com Tel: +44 (0) 114 281 2655
_______________________________________________________________
> -----Original Message-----
> From: owner-openrisc@o...
> [mailto:owner-openrisc@o...]On Behalf Of Brian Korsedal
> Sent: 28 August 2003 23:45
> To: openrisc@o...
> Subject: RE: [openrisc] Wishbone example and driver writing for uCLinux
> wishbone cores.
>
>
>
> O.K. Where would I go to learn how to write drivers for Linux?
> Do I need to write a device driver and patch it into the kernel,
> or can I just write a program and go through the /dev/ directory?
> Or is there a library used to output to the Wishbone bus?
>
> -Brian
>
> -----Original Message-----
> From: Damjan Lampret [mailto:lampret@o...]
> Sent: Thu 8/28/2003 10:24 AM
> To: openrisc@o...
> Cc:
> Subject: Re: [openrisc] Wishbone example and driver writing
> for uCLinux wishbone cores.
> Hi !
>
> Look at one of the IP cores that is WISHBONE compliant. To name a few:
> or1200, pci, ethernet, uart16550, ac97 etc.
>
> WISHBONE is transparent to software. Your software is the same
> regardless if
> you use WISHBONE as interconnect, or some other bus interconnect.
>
> regards,
> Damjan
>
> ----- Original Message -----
> From: "Brian Korsedal" <BKorsedal@b...>
> To: <openrisc@o...>
> Sent: Thursday, August 28, 2003 5:51 PM
> Subject: [openrisc] Wishbone example and driver writing for
> uCLinux wishbone
> cores.
>
>
> > Hi,
> >
> > Is there an example implimentation of the Wishbone
> architecture? What has
> > to be done to make a core Wishbone compatible?
> >
> > Also, Is there any manual on how to write drivers for cores on the
> Wishbone
> > bus? I've never written Linux drivers before.
> >
> > Thank you,
> >
> > Brian
> >
>
>
>
>
>
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