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Message
From: "#KUGAN VIVEKANANDARAJAH#" <kugan@p...>
Date: Sat, 30 Aug 2003 14:26:02 +0800
Subject: RE: [openrisc] Instruction Fetch
Thanks for the explanation,
>
> I'm not sure what you mean exactly but I'll tell you the following.
For
> example the code is being executed from an instruction cache, and if
there
> is an instruction cache miss, the pipeline will continue to execute
> instructions regardless it is waiting for instruction cache to
complete
> the
> cache line and start deliverting instructions to the pipeline. That
means
> while instruction cache is not delivering instructions, pipeline is
feed
> by
> NOPs.
In my case, the Instruction cache is not enabled, therefore it seems
like it is taking two cycles to fetch the instruction from memory, hence
the NOPs.
I am now trying to enable the Instruction cache, I compiled the basic
assembly programme in orp_soc with both I$ and D$ enabled. I am using
the or1k-elf- toolset from UC OpenRISC Project. However, the I$ is not
being enabled. i.e the ic_en in or1200_cpu is always zero. Did any one
has such problem?
Thanks in advance
Kugan
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