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From: Dries Driessens <ddr@d...>
Date: Tue, 26 Aug 2003 15:32:46 +0200
Subject: [openrisc] First hardware steps

Hello all

Yesterday I synthesised and compiled my first OR1200 for the Xess 
platform with Synplify and Xilinx ISE. Although I could get a connection 
using JP1-XESS with the ORP-SOC demo, I simply CAN'T get a connection 
with my own generated OR-system. Below are the steps that I followed.

Just to know: I synthesised the OR in synplify in just 2 minutes on a
P4-2,4GHz with 1GB DDR-RAM. Is this normal cause I read in messages that 
it takes 1 hour...
Synplify and ISE don't seem to optimize everything away:

Device utilization summary:

    Number of External GCLKIOBs         3 out of 4      75%
    Number of External IOBs           152 out of 166    91%
       Number of LOCed External IOBs    0 out of 152     0%

    Number of BLOCKRAMs                17 out of 28     60%
    Number of SLICEs                 6380 out of 9408   67%

    Number of GCLKs                     3 out of 4      75%
    Number of TBUFs                    64 out of 9632    1%

Anybody that succeeded in synthesizing and downloading their OR-system,
where did I do wrong?
Don't I have to initialize any block-RAMs or SRAMs?
Do I have to adjust any MHz or related defines in the verilog code?

I use xsv_cpld_2.svf for my cpld. Is this OK?

STEPS THAT I FOLLOWED:
----------------------
1) before running synplify, modify the synplify project file (
\or1k\xess\xsv_fpga\orp_soc\syn\synplify\xsv_fpga_top.prj ) :
* remove the 'add_file' lines of the (old) project files:
   - GENERIC_TPRAM.V
   - ETH_SYNC_CLK1_CLK2.V
   - ETH_WISHBONEDMA.V
   - GENERIC_SPRAM.V
   - UART_FIFO.V
* remove in every 'add_file' line: ../projects/xess/xsv_fpga/ from the path

2) disable the 'define SRAM_GENERIC in SRAM_TOP.V
(check there are no FLASH_GENERIC defined in FLASH_TOP.V)

3) change 'WB_ERR' into 'WB_ERR_O' in SRAM_TOP.V (line 348)

4) open synplify and run synthesis.

I noticed that the RTL directories contain several unused verilog files:
* all ..._DEFINES.V files weren't included because they don't
contain logic. I think are used because of the 'include "..." in the
verilog files.

* some files are simply unused because of certain 'defines', but might 
be useful in the future. Therefor I added them to the
synplify project for future versions:
   - OR1200_SB.V
   - OR1200_SB_FIFO.V
   - UART_TFIFO.V
   - UART_RFIFO.V
   - RAMINFR.V
   - ETH_SPRAM_256x32.V

* some files are completely unused and seemed to be unnecessary:
   - ETH_COP.V
   - PCI_USER_CONSTANTS.V
   - TOP.V

5) add the generated .edf file together with the correct .ucf file to a
Xilinx ISE project and run place&route

6) download .bit-file into the device.

Many thanks for any response!

Best regards,
Dries Driessens

----- Original Message -----
...
> I have added 256MB memory to my PC.now i have 512MB
> memory,but nothing changed.:(
>
> Kevin
...
> hi,all
> i have got the source code from the cvs,and changed
> the "xsv_fpga_top.prj" in the
> "xess\xsv_fpga\orp_soc\syn\synplify" to let
> synplify find the files.but when i synthezised it
> ,synplify
> told me several
> files couldn't be found.then i copy those files from
> ".old".this time
> synplify runs well.but complie takes such a long
> time!i
> waited half an
> hour and stop it.my PC is P4 2.4 and 256MB memory.can
> anyone tell me
> if this is normal?
>
> Kevin

...

> > I guess that sram memory are too much.
> >
> > Please comment a line "'define SDRAM_GENERIC" in
> > rtl/mem_if/sram_top.v
> > and retry.
> >
> > hy kim

Follow up Author

RE: [openrisc] First hardware steps Brian Adams