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Message
From: "Damjan Lampret" <lampret@o...>
Date: Mon, 25 Aug 2003 14:12:47 +0200
Subject: Re: [openrisc] OpenRISC targeted
Heya !
The complexity of system is increasing, so even if FPGAs density increases,
it doesn't change much. Remember, an equivalent ASIC to an FPGA can cost 10x
less than FPGA. If you have the volumes, you go with an ASIC. On the other
hand FPGAs are greate for prototyping, such as early software development
while you wait for the ASIC to come back from the fab, or for proof of
concept, and for products with low volumes.
Masks are getting more and more expensive. I think in the future there will
be more gate array like processes (.18um, .13um gate arrays). There are
already development in this direction. This will be a good bridge between
FPGAs and std cell ASICs, complemeting current ortfolio of gate arrays.
regards,
Damjan
----- Original Message -----
From: <ddr@d...>
To: <openrisc@o...>
Sent: Monday, August 25, 2003 1:43 PM
Subject: Re: [openrisc] OpenRISC targeted
> Dear Mr. Lampret
>
> I wouldn't describe the OpenRISC as a processor only for silicon in
> multi-million volumes. Even today and especially in the future, FPGA's
> will become increasingly more important because of:
> * REAL Low cost FPGA's like Altera Cyclone & Xilinx Spartan 3
> * Exponentially increasing cost of ASIC production (every new
> technology doubles the mask-cost)
>
> What is your opinion on this subject?
>
> Best regards,
> Dries Driessens
>
> ps: at the bottom, an article on the subject that I found at
> www.theinquirer.net
>
> ----- Original Message -----
> From: "Damjan Lampret" <lampret@o... >
> To: <openrisc@o... >
> Date: Mon, 23 Jun 2003 20:43:47 -0700
> Subject: Re: [openrisc] is Cray needed to synthesize ORP
>
> > In general, folks, look at what you are synthesizing. This sin't
> > meant to be "plug the files into synthesis tool and you will get
> > your PC out of it".
> > Remember OR1200 and perihperals used in orp_soc are targeted to
> > ASIC, not FPGA. FPGAs are merely to test stuff and as proof of
> > concept. Real use of the cores is in ASICs - read: silicon produced
> > in multimillion volumes at silicon foundries... You need at least 6+
> > months of experience doing synthesis on other designs, or you will
> > have to spend a few weeks to learn it and break a few teeth before
> > it will work for you. Considered you had been warned.
> >
> > regards,
> > Damjan
> >
>
>
> Electronic nanotechnology will sustain Moore's Law
>
> Up to a billion switches in a square centimeter
>
> By Mike Magee: Thursday 21 August 2003, 14:19
> A CARNEGIE MELLON professor said that field programmable gate array
> (FPGA) devices which use electronic nanotechnology and molecular
> electronics will keep Moore's Law alive and well in the future.
>
> Seth Goldstein, said the new class of electronics devices which is
> called chemically assembled electronic nanotechnology (CAEN) will be
> low power, defect tolerant and provide massive component densities at
> low cost in the future.
>
> Goldstein estimates that CAEN will allow improvements in computer
> power at orders of magnitude in the next 10 years, "without the huge
> upfront non-recoverable engineering costs of developing an ASIC device".
>
> He said that while there is still much research needed, CAEN may
> represent the most significant breakthrough in the chip industry since
> CMOS manufacturing technology was started in the 1960s.
>
> Such devices will be made from meshes of switches and wires, with a
> switch interconnecting each wire junction. Once programmed, he says, a
> switch will hold its state, can this will remove a lot of the overhead
> in traditional ICs.
>
> Up to one billion switches could be made on a single square
> centimetre, with CAEN being made using chemical self assembly
> techniques instead of photolithography.
>
> One architecture, called the Nanofabric, uses a hierarchical process
> to make the molecular switches, followed by two aligned groups of wire
> to make a two dimensional grid with the switches at the cross points.
> Separately, a silicon based die will use standard photolithography for
> power, clock lines, IO interface and support logic for the switch grids. ľ
>
> Š 2003 Breakthrough Publishing Ltd.
>
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