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Message
From: "Damjan Lampret" <lampret@o...>
Date: Fri, 22 Aug 2003 11:37:55 +0200
Subject: Re: [openrisc] Instruction Fetch
No.
regards,
Damjan
----- Original Message -----
From: "Mike Wiles" <mwiles@a...>
To: <openrisc@o...>
Sent: Friday, August 22, 2003 4:59 AM
Subject: Re: [openrisc] Instruction Fetch
> Damjan,
> Does the simulation model also model the floating point instructions
> and does it give accurate timing for them?
>
> Thanks,
> Mikew
>
>
> At 01:58 PM 08/21/2003 +0200, you wrote:
>
> >Heya !
> >
> >I'm not sure what you mean exactly but I'll tell you the following. For
> >example the code is being executed from an instruction cache, and if
there
> >is an instruction cache miss, the pipeline will continue to execute
> >instructions regardless it is waiting for instruction cache to complete
the
> >cache line and start deliverting instructions to the pipeline. That means
> >while instruction cache is not delivering instructions, pipeline is feed
by
> >NOPs.
> >
> >regards,
> >Damjan
> >
> >----- Original Message -----
> >From: "#KUGAN VIVEKANANDARAJAH#" <kugan@p...>
> >To: <openrisc@o...>
> >Sent: Thursday, August 21, 2003 11:59 AM
> >Subject: [openrisc] Instruction Fetch
> >
> >
> > >
> > > Hi again,
> > > I am simulating the orp_soc to see the instruction fetch architecture.
> > > It seems that instruction fetch is being stalled alternate clk cycle
and
> > > a NOP instruction is added by or1200_if. Is it because some thing is
> > > wrong with my or1200_defines ? Or is there any reason for this.
> > >
> > > Am I miss understanding it completely?
> > >
> > > Thanks in advance,
> > > Kuagn
> > >
> > >
> > >
> >
> >
> >
> >
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