|
Message
From: Philip Gutierrez <philip_gutierrez@y...>
Date: Sat, 9 Aug 2003 06:43:09 -0700 (PDT)
Subject: RE: [openrisc] Cell not translated
Sandeep,
I am new to the OR core, but I was unable to find any
file named RAMB* in the
.../OR1000/or1k/or1200/rtl/verilog source directory.
If you grep for RAMB you will find that RAMB4 is
instantiated in several files. I found no RAMB16
instantiation.
It seems like you are trying to synthesize a ram
simulation model. Had you gotten a 'unresolved
reference" error, then that would point to a missing
library. But you got an error for a tri net, so the
synthesis tool is trying to synthesize a model.
-philip
--- Richard Herveille <richard@a...> wrote:
> >
> > Richard: Have you been using Xilinx tools for
> synthesis of
> > OR1200? If so,
> > which libraries have you been using for the RAM
> blocks? I have
> > confirmed that tri0 net is unsupported in xst.
> >
> > Regards,
> > Sandeep.
>
> This didn't occur to me before, but it might be that
> you're looking in
> the wrong direction.
>
> 'tri0' is a verilog reserved keyword. It's a tri-net
> with a pull-down
> resistor model.
>
> Maybe that provides a clue?
>
> Richard
>
>
|
 |
Browse
