|
Message
From: "Damjan Lampret" <lampret@o...>
Date: Wed, 9 Jul 2003 00:03:11 -0700
Subject: Re: [openrisc] code tidyup
Matt,
thanks for the info. It seems most tools like Cadence NCsim, Synopsys Design
Compiler, Synplicity Synplify don't have a problem if a declaration is
missing. Anyway I'll add declarations to avoid any warnings.
regards,
Damjan
----- Original Message -----
From: <matt.gillespie@j...>
To: <openrisc@o...>
Sent: Tuesday, July 08, 2003 4:57 AM
Subject: [openrisc] code tidyup
> Are you aware that the or1200_top module has 3 wires not declared.
>
> I know that this is legal but you do list all other single wires.
>
> the missing wires are :
>
> icbiu_cab_ic
> icpu_rty_immu
> dcpu_cycstb_cpu
>
>
>
|
 |
Browse
