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Message
From: Soban Shoeb Chawre <sobanc@n...>
Date: Fri, 27 Jun 2003 23:22:41 +0530
Subject: Re: [openrisc] Cache Line Fill
Hello All,
Will some 1 plz tell me
1.how many K gates FPGA is needed for implementing ORP SOC ?
2.What are Memory requirements (I mean size of EPROM, Flash and
SRAM/SDRAM) for ORP SOC design development board?
Regards,
-Soban
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