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Message
From: Marko Mlinar <markom@o...>
Date: Thu, 26 Jun 2003 07:59:13 +0200
Subject: Re: [openrisc] about cache scheme
On Thursday 26 June 2003 03:31, zhustudio wrote:
> hi all,
>
> i have find if you enable cache in compile stage, and then sim in or1200
> soc platform, the instruction cache is enabled between 63400ns, and the
> instruction is l.mtspr r0,r10,0x11, diassemble is 0xc0005011. i have test
> many programs that are provided in sw directory. so can anyone tell me why
> perform this sheme? is it a program compiler option or others. thank you
If I understood you correctly, you are referring to bit in the SR, which
allows you to enable/disable cache. All CPUs have this functionality.
This instruction is usually specified in your loader program, e.g. reset.S
Marko
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