|
Message
From: "zhustudio" <zhustudio@i...>
Date: Thu, 26 Jun 2003 9:31:40 +0800
Subject: [openrisc] about cache scheme
hi all,
i have find if you enable cache in compile stage, and then sim in or1200 soc platform, the instruction cache is enabled between 63400ns, and the instruction is l.mtspr r0,r10,0x11, diassemble is 0xc0005011. i have test many programs that are provided in sw directory. so can anyone tell me why perform this sheme? is it a program compiler option or others. thank you
Jiahui Zhu
Email: zhustudio@i...
Date: 2003-06-26
|
 |
Browse
