|
Message
From: "Jerry English" <jenglish@w...>
Date: Thu, 22 May 2003 10:53:04 -0400
Subject: [openrisc] Request clarification
Greetings,
I am attempting to put the ORP SOC into an Altera FPGA. I eliminated some of the modules, VGA and audio come to mind.
I was getting a "strange" error message from Quartus II verilog compiler about not being able to process inverted tri state primitives.
After tracking this down to the flash_top.v module I observed that the `include bench_define.v had been commented out. Then searching for
the definition of FLASH_GENERIC and FLASH_GENERIC_REGISTERED I found that these were not defined anywhere. I am wondering why
this is done in this manner.
In order to get around the error message I commented out that section of code within the undefined FLASH_GENERIC and FLASH_GENERIC_REGISTERED. The code did compile. Clock speed is around 14 Mhz. The bottleneck appears to be in the
ALU shift operation.
Regards
Jerry
|
Browse
