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    Navigation: All forums > Openrisc > Message List > Message Post

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    From: Marko Mlinar <markom@o...>
    Date: Thu, 22 May 2003 09:31:08 +0200
    Subject: Re: [openrisc] Question) Address transfer between IMMU & ICache
    Top

    Jim,
    
    We would really appreciate if you can provide a simple testcase, that fails 
    with latest CVS version. It would be nice also if you can also send a defines 
    file.
    
    thanks,
    Marko
    
    
    On Thursday 22 May 2003 05:12, Jim Tong wrote:
    > Damjan:
    >    We are using the latest version. The problem shows
    > up very quickly when we run interrupt driven programs.
    > The basic problem is Icache controller used an old
    > address even when CPU switched to a new address.
    >
    > Jim
    >
    > --- Damjan Lampret <lampret@o...> wrote:
    > > Hi !
    > >
    > > I'd like to know more so in case there is a problem
    > > it can be fixed.
    > >
    > > Obviously I have not seen this problem before and if
    > > it would most of the
    > > more complex software wouldn't work as jumps are
    > > pretty common ;-)
    > >
    > > Also I doubt that uClinux would work with such very
    > > basic bug. uClinux makes
    > > many exceptions.
    > >
    > > regards,
    > > Damjan
    > >
    > > PS Make sure you don't use an old version. Verify
    > > your source files againt
    > > the one in the cvs. Or better, take the latest from
    > > the CVS.
    > >
    > > ----- Original Message -----
    > > From: "Jim Tong" <jtong@r...>
    > > To: <openrisc@o...>
    > > Sent: Tuesday, May 20, 2003 10:42 PM
    > > Subject: Re: [openrisc] Question) Address transfer
    > > between IMMU & ICache
    > >
    > > > Sungyon:
    > > >    I saw many similar problems. When jump or
    > >
    > > exception
    > >
    > > > happened, the Icache returned the old data. My
    > > > recommendation is to design your own cache
    > >
    > > controller.
    > >
    > > > Jim
    > > >
    > > > --- SUNGYON@a... wrote:
    > > > > Dear Lampret & members,
    > > > >
    > > > > I'm doing MP3 RTL simulation in or1k/mp3
    > >
    > > directory.
    > >
    > > > > It seems that The MP3 draft is concuded with
    > >
    > > ICache
    > >
    > > > > disabled.
    > > > > I enabled the ICache, and run the minimad but
    > >
    > > this
    > >
    > > > > failed.
    > > > >
    > > > > Through the waveform analysis, on the occurrence
    > >
    > > of
    > >
    > > > > address jump,
    > > > > I found that the communication between IMMU &
    > >
    > > ICache
    > >
    > > > > seems to have a
    > > > > problem.
    > > > >
    > > > > For example, for 4k ICache & IMMU disabled
    > > > > on the jump from 8000-8758 to 8000-a708
    > > > > Since IMMU provides 8000-8708 (which is
    > >
    > > {previous
    > >
    > > > > tag range(8000-8),
    > > > > current index(708 of 8000-a708)}) to ICache,
    > > > > The Icache decides hits with 8000-8708 and the
    > > > > 8000-8708 is executed
    > > > > really. It's wrong.
    > > > > The executed.log shows that 8000-a708 is
    > >
    > > executed
    > >
    > > > > with instruction of
    > > > > 8000-8708.
    > > > > For summary, IMMU does not be prividing right
    > > > > address to ICache.
    > > > >
    > > > > I think it's difficult to talk about this
    > >
    > > problem in
    > >
    > > > > detail, since we are
    > > > > not in one desk.
    > > > > But If anyone haves any helpful idea about this,
    > > > > give me.
    > > > > Thank you in ahead.
    > > > >
    > > > > Regards, Sungyon in South Korea.
    > > > >
    > > > >
    > > > >
    > > > > --
    > > > > To unsubscribe from openrisc mailing list please
    > > > > visit
    > >
    > > http://www.opencores.org/mailinglists.shtml
    > >
    > > > --
    > > > To unsubscribe from openrisc mailing list please
    > >
    > > visit
    > > http://www.opencores.org/mailinglists.shtml
    > >
    > >
    > > 
    
    
    
    
    

    ReferenceAuthor
    Re: [openrisc] Question) Address transfer between IMMU & ICacheJim Tong

     
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