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Message
From: Michael Unneback <michael@h...>
Date: Tue, 20 May 2003 19:16:10 +0200
Subject: Re: [openrisc] ORP SOC synthesis
Hi,
here is some script files for the synthesis of OR1200 with XST running
in batch mode. I do not remember if I used them with XST release for 4
or 5. Some minor changes might have to be done. One thing is the syntax
for choosing target type.
FYI: I used these files a while ago. When using xilinx version 4 my
design worked without problem. When I switched to release 5 I discovered
some problems. I did not have time to look deeper into this at the time.
The problem seem to relate to either the wishbone bus arbiter, the UART
or OR1200.
Extract zip file to or1200/syn. Run make_or1200.bat in library run. Enjoy.
regards
/Michael Unneback
Jerry English wrote:
>I started off by trying to get Quartus to synthesize the soc. Since I was targeting Stratix I had to make the necessary memory models.
>To make a long story short..Quartus found several areas of code that it could not handle. OK so now I've switched back to the xilinx soc based
>system. I am trying to compile the soc using xilinx xst in the command line mode. XST gets to the or1200_tpram_32x32.v file then
>complains about the port sizes not being the same width. Well that's correct since the model has a 8 bit wide address bus and the calling
>module is passing a 5 or 6 bit wide address.
>
>Has anybody complied the SOC using XST and if so would you share your script file?
>
>Thanks
>Jerry
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xst.zip
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