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    Navigation: All forums > Openrisc > Message List > Message Post

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    From: "Jerry English" <jenglish@w...>
    Date: Tue, 20 May 2003 12:05:04 -0400
    Subject: [openrisc] ORP SOC synthesis
    Top

    I started off by trying to get Quartus to synthesize the soc. Since I was targeting Stratix I had to make the necessary memory models.
    To make a long story short..Quartus found several areas of code that it could not handle. OK so now I've switched back to the xilinx soc based
    system. I am trying to compile the soc using xilinx xst in the command line mode. XST gets to the or1200_tpram_32x32.v  file then
    complains about the port sizes not being the same width. Well that's correct since the model has a 8 bit wide address bus and the calling
    module is passing a 5 or 6 bit wide address. 
    
    Has anybody complied the SOC using XST and if so would you share your script file?
    
    Thanks
    Jerry
    
    
    
    
    

    Follow upAuthor
    Re: [openrisc] ORP SOC synthesisMichael Unneback

     
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