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Message
From: "Jerry English" <jenglish@w...>
Date: Thu, 15 May 2003 11:34:46 -0400
Subject: [openrisc] sram_top.v
Greetings,
I am trying to compile the SOC for Altera's Stratix. I have made many many memory
models. Now I am looking at the file mem_if/sram_top.v.
At first the sram_top.v caused an internal error in quartus. I commented out the `define SRAM_GENERIC in the sram_top.v file.
Now Quartus is complaining about an undefined variable wb_err.
I copied assign wb_err = wb_cyc_i & wb_stb_i & (delay == 2'd0) & (|wb_adr_i[23:21]); to the `else module but
got another error message about delay not being defined.
So at this point I'm pretty uncomfortable about copying, commenting and pasting into code that I
know next to nothing about.
I would have thought that just commenting out the `define SRAM_GENERIC would have done the trick.
Where did I go wrong?
regards
Jerry
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