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Message
From: "Damjan Lampret" <lampret@o...>
Date: Wed, 30 Apr 2003 20:58:10 -0700
Subject: Re: [openrisc] Connect to JTAG, then?
----- Original Message -----
From: <reanphoto@y...>
To: <openrisc@o...>
Sent: Tuesday, April 29, 2003 10:37 PM
Subject: Re: [openrisc] Connect to JTAG, then?
> Hi Damjan,
>
> Thanks for youe reply.
>
> I have some detail question,
>
> 1. In the "xsc_fpga_top.v" I see a module named "tc_top", it looks like
> a test module, should I remove/mark it when I want to synthesis for
> FPGA?
This is "traffic cop". It integrates all different IP blocks in the "SoC".
You can't remove it if you want to use orp_soc (as it integrates all
internal blocks together...).
>
> 2. I use the prepared files "xsv_fpga_top_ethernet.exo"
> and "xsv_cpld_2.svf" for the flash and CPLD, and
> a. What frequency should I set for FPGA?
IIRC 10 MHz. It has been a while I played with XSV800.
> b. Which ORPmon file should I use, "orpmon.or32" or "orpmon-
> flash.or32"?
Can't remember, try both.
> c. What is the setting of the terminal(e.g. baud rate, parity...) to see
> the ORPmon console?
Either 9600 or 19200. But the rest is 8N1 for sure.
> d. After connect the uart, initial the terminal, Am I just waiting the
> prompt?
Yes. Just send the CR to update the prompt.
regards,
Damjan
>
> Thanks you, and I would add the information if I success my
> implementation.
>
> reanphoto
>
>
>
> ----- Original Message -----
> From: "Damjan Lampret" <lampret@o... >
> To: <openrisc@o... >
> Date: Tue, 29 Apr 2003 16:16:49 -0700
> Subject: Re: [openrisc] Connect to JTAG, then?
>
> >
> >
> > Heya !
> >
> > 1) You probably use generic memories (just a guess why it takes so
> > much
> > time). Make sure you target it to Xilinx Virtex if you want to use
> > Xess
> > XSV800 boards. Also on slow computer synthesis can take hours.
> > 2) Console is available on RS232 port of XSV board. Connect a
> > terminal to
> > RS232 port (you can use a PC with Hyper Terminal software).
> > 3) There is a README file but chapter about synthesis is empty.
> > I'll add
> > something in the future or you can add something if you will do
> > synthesis/implementation for XSV.
> >
> > regards,
> > Damjan
> >
> > ----- Original Message -----
> > From: <reanphoto@y... >
> > To: <openrisc@o... >
> > Sent: Tuesday, April 29, 2003 5:13 AM
> > Subject: [openrisc] Connect to JTAG, then?
> >
> >
> > > Hi everyone,
> > >
> > > Thanks for the OpenRISC project, it's really a good project,
> > well done.
> > >
> > > I am begin to try the xess version, I have some questions,
> > please help
> > > me if somone know how to solve them, thanks
> > >
> > > 1. I try to synthesis the 'xsv_fpga_top.prj' by synplify pro
> > 7.2.3, but it
> > > seems never end, always stay at 'compiling' stage, what's
> > going on?
> > >
> > > 2. I load the 'xsv_fpga_top_ethernet.exo' into Flash memory,
> > and
> > > connect the JTAG server through gdb, load the ORPmon, use the
> > > commands as the web page says, after command 'c', what should
> > I do?
> > > how to display the ORPmon console?
> > >
> > > 3. Is there any document about synthesis, implementation
> > hardware,
> > > then use some software tools to communication to the FPGA
> > board step
> > > by step?
> > >
> > > thanks a lot.
> > >
> > > reanphoto
> > >
> > >
> >
>
>
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