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From: brantley@m...
Date: Wed, 23 Apr 2003 02:12:28 -0100
Subject: Re: [openrisc] OpenRisc and ModelSim/Xst

I had forgotten about that problem until you mentioned it.
I am not an xst expert myself. It seems that xst has a problem 
with the module name getting wrapped in an ifdef.  I tried 
putting the def and module name on the same line thinking it might 
be a line feed problem, but that made no difference. Basically I just 
had to comment out all the module names and defs except the one one I
was interested in as you see below.

I am not sure what a real solution would be.

In the end it made  no difference because I had to remove all the
caches so the cpu could fit on my 300k spartan.

If you still need my project files to resolve other problems I can
supply that. It is about 12Meg for the whole Project Navigator archive.

//
// Instantiation of IC RAM block
//
//`ifdef OR1200_IC_1W_4KB 
or1200_spram_1024x32 ic_ram0( 
//`endif
//`ifdef OR1200_IC_1W_8KB 
//or1200_spram_2048x32 ic_ram0( 
//`endif
`ifdef OR1200_BIST
	// RAM BIST
	.scanb_rst(scanb_rst),
	.scanb_si(scanb_si),
	.scanb_so(scanb_so),
	.scanb_en(scanb_en),
	.scanb_clk(scanb_clk),
`endif
	.clk(clk),
	.rst(rst),
	.ce(en),
	.we(we[0]),
	.oe(1'b1),
	.addr(addr),
	.di(datain),
	.do(dataout)
);