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Message
From: mrmclean@c...
Date: Tue, 22 Apr 2003 22:33:16 -0100
Subject: [openrisc] memory question
All,
I'm converting the SOC demo that ran on the XVS-800 to a FPGA board
that has only SRAM (similar to the Avnet board). I looked through the
verilog at the top level and noticed it was changing the flash prefix for
decoding flash accesses. I am still not sure of the big picture here, is
the xess demo running from flash and the sram is used for data?
Thanks
Mark
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