LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Find Resources
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Openrisc > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: "Damjan Lampret" <lampret@o...>
    Date: Tue, 22 Apr 2003 13:00:42 -0700
    Subject: Re: [openrisc] OpenRisc and ModelSim/Xst
    Top

    > no external memory and needed the block memory for other things. So I used
    > the generic registers.
    > However these never get initialized in running with model sim, so the
    > registers are stuck with an unknown
    > value and the simulation goes no where. So I added in the following
    
    Damon,
    
    in OR1200 implementation there is no logic that would reset GPRs at reset
    (to make design simpler). Instead a different approach has been taken. Reset
    vector SW code sets all registers to zero. You can see this in reset vector
    in all test cases, orp_mon, uclinux etc.
    
    Note: GPR[0] can only be written once. It should be set to zero. After first
    write it is no longer possible to change GPR[0] to ensure compliance with
    architecture model where GPR[0] is always fixed to zero.
    
    regards,
    Damjan
    
    
    
    
    

    ReferenceAuthor
    [openrisc] OpenRisc and ModelSim/XstDamon Brantley

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.