OPENCORES.ORG

From: marcus.erlandsson at opencores.org<marcus.erlandsson@o...>
Date: Wed Oct 1 17:10:02 CEST 2008
Subject: [oc] a VHDL 16550 UART core & Wishbone LPC Host and Peripheral Bridge

Hi Matt, Please send an email to the maintainer/s of this cores and describe the issue so that it can be upgraded/fixed. It is very important that we track potential bugs. Regards Marcus ----- Original Message ----- From: Matt Ettus<matt@e...> To: Date: Wed Oct 1 08:14:02 CEST 2008 Subject: [oc] a VHDL 16550 UART core & Wishbone LPC Host and Peripheral Bridge > Thomas at opencores.org wrote: > > Hi! > > > > I have a problem when implementing the 16550 UART together > with the wb > > to lpc peripheral (using gh_vhdl_lib). I use a Endura TP945 > board as a > > host and implement the design on a xilinx starter board. The > problem > > is that when I try to read from the MSR register the data is > wrong and > > the other registers is resetted. If the register is set to a > constant > > value, everything works fine. If, for example (for bit 0 in > the MSR > > register) the value in to the jkff is set to a constant '0', > > everything works fine. But otherwise, the iDCTS goes high > during a > > read, indicating that the value on CTSn has changed (CTSn is > set to '1'). > > This is not really a big problem since the register is not > used, but I > > would really like to understand this. > > I have also tried to implement extra wait states without > result. > > > I have found several problems in that core, but I didn't notice the > issues you have. You can get my fixed version here: > svn co > > http://gnuradio.org/svn/gnuradio/trunk/usrp2/fpga/opencores/uart16550 > Among the bugs are problems with the FIFOs and a bad wishbone > interface. > Matt > >