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Message
From: Klaus.Rindtorff at googlemail.com<Klaus.Rindtorff@g...>
Date: Fri Aug 8 18:30:13 CEST 2008
Subject: [oc] DDR IP for Spartan 3E Xilinx evakit
Hi Jörg, I'd love to use your controller, but it is written in
Verilog. I just got used to VHDL and don't want to switch back. I
believe I saw a VHDL version in your download section some month ago,
but it seems they it was removed since then.
This is so frustrating: I have a working CPU and tool-chain in my
software simulation, but mess around with the DDR memory of the Xilinx
S3E board for months now...
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