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From: Klaus.Rindtorff at googlemail.com<Klaus.Rindtorff@g...>
Date: Wed Jul 30 20:29:43 CEST 2008
Subject: [oc] DDR IP for Spartan 3E Xilinx evakit
Hi Steve, many thanks. I will give your code a try immediately.
Is there a description of the mem_ctrl interface signals available?

When looking at the implementation I am missing the typical 200 us
wait for the SDRAM, but found a reference to DdrInit(). I guess that
means that the CPU is responsible to create a memory access pattern
during startup that will initialize the chip, correct?

- Klaus