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Message
From: chen.z at opencores.org<chen.z@o...>
Date: Wed Jul 30 16:10:46 CEST 2008
Subject: [oc] DDR IP for Spartan 3E Xilinx evakit
Read for ddr is little complex,
you should check the data path,
maybe timing for logic is OK,(I didn't read code yet)
In FPGA your also need to check detail timing , ucf ,etc.
On chip debug is via by chipscope from Xilinx.
Good Luck.
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