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Does Xilinx document their data file for their chips? Suppose I wanted

dashxdr@g... wrote:
> Does Xilinx document their data file for their chips? Suppose I wanted
> to write a place & route program to generate the datafile, it'd be
> possible if I knew the format and how the bits all get ordered on the
> device.

As far as I know, the details of the datafile formats are kept secret by 
the FPGA vendors (maybe with the exception of some very old device 
families). At least this was true a few years ago, please correct me if 
I'm wrong.

I guess that there are at least two reasons for the secrecy:

1. The FPGA vendors would want to minimize the risk of giving away any 
of their intellectual property, the core of their business, for free to 
the competition.

2. It would probably be quite cumbersome and resource-demanding for them 
  to publish this info, as it would imply producing release-grade 
characterization and documentation of every little gory detail of the 
inner workings of the FPGAs, including timing, power etc. It might 
further generate demand for lots of support.

But maybe one of the smaller FPGA companies would consider it an 
advantage to publish this some day, that would be interesting!

Best regards
Gunnar Dahlgren

> 
> Thanks--
> Dave
> 
>> All we have today is the limited performance of FPGA EDA tools
>> because
>> of its closed source nature.
>> Regards,
>> Vadim Kataev
>>
>>
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