LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Sponsors
  • Mirrors
  • Logos
  • Contact us
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cores > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: Klaus.Rindtorff at googlemail.com<Klaus.Rindtorff@g...>
    Date: Mon Jul 28 08:31:16 CEST 2008
    Subject: [oc] DDR IP for Spartan 3E Xilinx evakit
    Top
    Hi Alessandro, we have the same goal: using the DDR SDRAM on the S3E
    board. So far I am trying to make the Opencores DDR_SDR core from this
    site work for me. Writes are ok, but I still have problems with reads
    in some circumstances. Your other option would be to use MIG from the
    ISE SDK to generate a core for you. I didn't try that yet as the
    generated core looks too complicated to me.

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.