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    Navigation: All forums > Cores > Message List > Message Post

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    From: andrew mulcock<spam@m...>
    Date: Fri Jul 11 19:28:34 CEST 2008
    Subject: [oc] DDR IP for Spartan 3E Xilinx evakit
    Top

    And

    I'd imagine the Edk you have on disk is an eval version, they normally are
    as EDK costs extra.

    If you did pay for EDK, then you get one year of update, so you could then
    update to latest EDK.

    Xilinx certainly used to provide BDF's,
    for instance this is the link to the reference designs for one of
    the Xilinx boards I use.

    http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm


    Andrew



    -----Original Message-----
    From: cores-bounces@o... [mailto:cores-bounces@o...] On
    Behalf Of Alessandro
    Sent: 10 July 2008 22:23
    To: Discussion list about free open source IP cores
    Subject: [oc] DDR IP for Spartan 3E Xilinx evakit


    Hi everybody!

    I'm working at this enhanced ZX-Spectrum clone (ZX-Badaloc) project:
    http://www.zxbada.bbk.org/badaloc_fpga/index.htm and, thanks to the support
    about the T80 core of Mike Johnson, who suggested a workaround for timing
    problem (using the fpgaarcade's pacman T80 wrapper), it is possible to run
    the clone on the Spartan 3E evaluation board (downloadable file available).

    I'm using the internal blockram of the fpga, but the next step would be
    accessing the on-board DDR chip and to implement all the advanced memory
    features of the original clone (that I made using a XPLA3 cpld a couple of
    years ago).

    The problem is: is there a way to istantiate a DDR controller which matches
    the ddr chip installed on this board without getting mad? I've been trying
    in many ways; maybe I need to install the EDK that comes with the board, but

    the problem is: I started the project on ISE 10 and I don't want to
    downgrade it to 9 (which is the version of EDK on my Xilinx DVD).
    Furthermore, I'm not even sure this would solve the problem.

    I'm new to fpgas, I found a way to istantiate block ram, the DCM for 85MHz,
    the T80 processor... but this time I'm stuck. I see there are ddr
    controller's IP here and there but it seems a complex matter to me. I can't
    believe xilinx does not provide one ready to use for this board... am I
    wrong?

    If someone could help me, we may see a 64megabyte 42.5MHz ZX-Spectrum soon
    :-)

    Thanks in advance and Best Regards
    Alessandro

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    ReferenceAuthor
    [oc] DDR IP for Spartan 3E Xilinx evakitAlessandro

     
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