OPENCORES.ORG

Mode is just a definition here;

Hi Richard,
Thank you for your answer.
I just want to make sure I understood this correctly.
Does it mean that for highspeed I need to program the divider after the 
arbitration stage(master_code)? - meaning that I need to set EN bit to 0
(disable core) and after that set prescale register again to higher 
frequency?
omer

----- Original Message ----- 
From: Richard Herveille<richard@h...> 
To: 
Date: Wed Jul  9 17:11:40 CEST 2008 
Subject: [oc] i2c speed - for master core 

> Mode is just a definition here; 
> 0-100kHz SCL clock: normal 
> 100kHz-400kHz SCL clock: fast 
> 400kHz-(3.5MHz) SCL clock: high speed 
> For the core there's no difference, just program the divider to 
> achieve the 
> desired frequency. 
> >From a pad perspective there might be a difference; Phillips 
> specified a 
> different pad type for the high speed devices. Although you might 
> achieve 
> good results using normal pads. 
> Richard 
> -----Original Message----- 
> From: cores-bounces at opencores.org [mailto:cores-bounces at 
> opencores.org] On 
> Behalf Of omer_pessach at lucidlogix.com 
> Sent: 09 July 2008 11:13 
> To: cores at opencores.org 
> Subject: [oc] i2c speed - for master core 
> Hi, 
> I looked in your i2c master core and according to the spec it is 
> supporting all different speeds - normal,fast and high_speed. 
> One thing that I did not understand is how changing of speed is 
> done in 
> your implementation and how can the user program the master to 
work 
> in each one of the speeds. 
> Can you elaborate on this? 
> This would help me a lot. 
> Thank you, 
> omer pessach 
> _______________________________________________ 
> http://www.opencores.org/mailman/listinfo/cores 
> 
> 