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Message
From: Fabien Marteau<fabien.marteau@l...>
Date: Mon Apr 14 10:21:09 CEST 2008
Subject: [oc] i2c ocore linux driver.
>So the interface remains 8bit, then how can you write 16bits?
I configured SEL pins on top component : SEL<= "11"
>Oh and you might want to change the lines
> SCL <= SCLo when (SCLo = '0') else 'Z';
> SDA <= SDAo when (SDAo = '0') else 'Z';
>
>To
>
> SCL <= '0' when (SCLo = '0') else 'Z';
> SDA <= '0' when (SDAo = '0') else 'Z';
I changed these lines, and I ve got the same result. Scope traces can be
seen here : attachment.htm>:
> >
> >
> >
> >
> > The core never releases SDA and SCL at the same time.
> >
> > The order you specified sounds fine and it works on the 8bit interface.
> >
> > Are you sure you didn't break anything when you modified the 8bit
> interface to a 16bit interface?
> >
> >
> >
> > Richard
> >
> >
> >
> >
> >
> >
> > From: attachment.htm]
> On
> Behalf Of Fabien Marteau
> > Sent: 08 April 2008 11:41
> > To: attachment.htm
> > Subject: [oc] i2c ocore linux driver.
> >
> >
> >
> > Hello,
> >
> > I integrated the i2c ocore IP(VHDL) in a design with other Wishbone IP
> and
> a irq manager core.
> >
> > The FPGA (spartan3) is connected to an ARM-processor (imx) with linux as
> operating system ( attachment.htm).
> >
> > With my design, I only can read/write in 16bits data bus mode (with
> sel=11). Then I write on register TXR and CR at the same time for example.
> Reading the VHDL
> > IP code I found these address decode:
> >
> > ----------------------------------
> > RXR | SR | 11
> > TXR | CR | 10
> > | CTR | 01
> > PRERhi | PRERlo | 00
> > ----------------------------------
> >
> > To test this core, I branched an accelerometer on i2c bus (address 0x1d)
> and I read/write on the same register (0x16). Then I wrote a simple proc
> driver that do :
> >
> > #unmask interrupt for i2c in interrupt manager:
> > write 0x0002 in IRQ_MASK
> > #Configure i2c speed prescaler (100kHz, FPGA clock is 96MHz)
> > write 0x00bf in PRESCALER (address 00)
> > #Enable core and enable interruption
> > write 0x00c0 in CTR (address 01)
> > #send start and address in write mode (address 0x1d<<1) and acknowledge
> interrupt
> > write 0x3a91 in TXR_CR (address 10)
> > ---- wait for interruption
> > #send subaddress, ackowledge core interrupt an set WR
> > write 0x1611 in TXR_CR (address 10)
> > #acknowledge interruption on my irq_mngr
> > write 0x0002 on IRQ_ACK
> > ---- wait for interruption
> > # write the value (0xbb) set stop bit wr bit and acknowledge
> interruption
> > write 0xbb51 on TXR_CR (address 10)
> > --- wait for interruption
> > #set stop bit and acknowledge interruption
> > write 0x0041 on TXR_CR (address 10)
> > #acknowledge interruption on my irq_mngr
> > write 0x0002 on IRQ_ACK
> >
> > That work well but, when I write for read at the same subaddress with :
> >
> > #send address 0x1d, set write bit set start bit and acknowledge
> interrupt
> > write 0x3a91 in TXR_CR (address 10)
> >
> > And I look traces on scope I see no start condition. SDA and SCL are
> switching to 0 at the same time. It's ok to read, the component return the
> good value, but this can be a problem for some components.
> >
> > Is somebody has this problem, or do you think it is a wrong programming
> ?
> >
> > I saw there is a linux driver for this core but, of course, without
> irq_mng and with 8bit write. I will try to modify it to read/write in
> 16bits.
> >
> > Thanks
> >
> > Fabien M
> >
> >
> > _______________________________________________
> > attachment.htm
> >
> _______________________________________________
> attachment.htm
>
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> 09:17
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> _______________________________________________
> attachment.htm
>
> _______________________________________________
> attachment.htm
>
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