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Re 
WARNING:Xst:646 - Signal <txd> is assigned but never used
Check the ise warnings, you'll probably find that the signal either has no
used output, so is 'pruned' by the optimiser, or the sensitivity list is
wrong, meaning the signal was not used in a equation and again optimised
out.

You really should have no sensitivity list warnings, if you do different
tools can and do do different things, 

Oh and you might want to change the lines

	SCL <= SCLo when (SCLo = '0') else 'Z';
	SDA <= SDAo when (SDAo = '0') else 'Z';

To

	SCL <= '0' when (SCLo = '0') else 'Z';
	SDA <= '0' when (SDAo = '0') else 'Z';

No great reason than I'd like it that way and I think compilers find it
easier to work with, they are assigning a level not an equality. Should in
the end be the same output, but I work on the preemies that the easier you
make it for the compilers the more likely you are to get what you want.

Andrew Mulcock

-----Original Message-----
From: cores-bounces@o... [mailto:cores-bounces@o...] On
Behalf Of Fabien Marteau
Sent: 10 April 2008 08:50
To: Discussion list about free open source IP cores
Subject: Re: *** PROBABLY SPAM *** RE: [oc] i2c ocore linux driver.

Thanks for your quick response.

I used this VHDL file :
http://www.opencores.org/cvsweb.cgi/~checkout~/i2c/vhdl/Attic/wishbone_i2c_m
aster.vhd?rev=1.1;content-type=text%2Fplain

And I just changed this line :
ADR_I : in unsigned(1 downto 0); -- lower address bits
with
ADR_I : in std_logic_vector(1 downto 0);		-- lower address
bits

And I added some signals on process sensivity list:
ocess(clk, nReset, state, dcnt,
core_txd,core_cmd,go,start,read,core_ack,sr,ack_in,stop)
[...]
nxt_state_decoder : process (clk, nReset, state, cmd,txd,Din)
[...]
output_decoder: process (clk, nReset, state,SCLo,sSDA,Din)

To synthetize with less warning.

And I added these lines in my top component :

	SCL <= SCLo when (SCLo = '0') else 'Z';
	SDA <= SDAo when (SDAo = '0') else 'Z';
	SCLi <= SCL;
	SDAi <= SDA;

I've got some warning in synthesis with xst:

WARNING:Xst:646 - Signal <txd> is assigned but never used.
WARNING:Xst:646 - Signal <we_a3> is assigned but never used.

The first warning is strange, because in VHDL txd *is* assigned.

FabM

2008/4/9 Richard Herveille <richard@h...>:
>
>
>
>
> The core never releases SDA and SCL at the same time.
>
> The order you specified sounds fine and it works on the 8bit interface.
>
> Are you sure you didn't break anything when you modified the 8bit
interface to a 16bit interface?
>
>
>
> Richard
>
>
>
>
>
>
> From: cores-bounces@o... [mailto:cores-bounces@o...] On
Behalf Of Fabien Marteau
> Sent: 08 April 2008 11:41
> To: cores@o...
> Subject: [oc] i2c ocore linux driver.
>
>
>
> Hello,
>
> I integrated the i2c ocore IP(VHDL) in a design with other Wishbone IP and
a irq manager core.
>
> The FPGA (spartan3) is connected to an ARM-processor (imx) with linux as
operating system ( http://www.armadeus.com).
>
> With my design, I only can read/write in 16bits data bus mode (with
sel=11). Then I write on register TXR and CR at the same time for example.
Reading the VHDL
> IP code I found these address decode:
>
> ----------------------------------
> RXR       |  SR      | 11
> TXR       |  CR      |  10
>              |  CTR     | 01
> PRERhi | PRERlo | 00
> ----------------------------------
>
> To test this core, I branched an accelerometer on i2c bus (address 0x1d)
and I read/write on the same register (0x16). Then I wrote a simple proc
driver that do :
>
> #unmask interrupt for i2c in interrupt manager:
> write 0x0002 in IRQ_MASK
> #Configure i2c speed prescaler (100kHz, FPGA clock is 96MHz)
> write 0x00bf in PRESCALER (address 00)
> #Enable core and enable interruption
> write 0x00c0 in CTR (address 01)
> #send start and address in write mode (address 0x1d<<1) and acknowledge
interrupt
> write 0x3a91 in TXR_CR (address 10)
> ---- wait for interruption
> #send subaddress, ackowledge core interrupt an set WR
> write 0x1611 in TXR_CR (address 10)
> #acknowledge interruption on my irq_mngr
> write 0x0002 on IRQ_ACK
> ---- wait for interruption
> # write the value (0xbb) set stop bit wr bit and acknowledge interruption
> write 0xbb51 on TXR_CR (address 10)
> --- wait for interruption
> #set stop bit and acknowledge interruption
> write 0x0041 on TXR_CR (address 10)
> #acknowledge interruption on my irq_mngr
> write 0x0002 on IRQ_ACK
>
> That work well but, when I write for read at the same subaddress with :
>
> #send address 0x1d, set write bit set start bit and acknowledge interrupt
> write 0x3a91 in TXR_CR (address 10)
>
> And I look traces on scope I see no start condition. SDA and SCL are
switching to 0 at the same time. It's ok to read, the component return the
good value, but this can be a problem for some components.
>
> Is somebody has this problem, or do you think it is a wrong programming ?
>
> I saw there is a linux driver for this core but, of course, without
irq_mng and with 8bit write. I will try to modify it to read/write in
16bits.
>
> Thanks
>
> Fabien M
>
>
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
>
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

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