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    Navigation: All forums > Cores > Message List > Message Post

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    From: Richard Herveille<richard@h...>
    Date: Fri Mar 28 16:07:15 CET 2008
    Subject: [oc] Integrate I2C core into FPGA
    Top
    Get a hold of the Wisbone SoC Interconnect document.
    It is posted on the opencores website.

    Wishbone is a pretty straightforward interconnect.
    Most of the names should be self explanatory.

    The i2c master provided on opencores should do just fine what you need.
    However it is only an i2c interface. It requires a controller (statemachine,
    cpu, whatever) to program the i2c master.

    Richard



    -----Original Message-----
    From: cores-bounces@o... [mailto:cores-bounces@o...] On
    Behalf Of dslaman0877@y...
    Sent: 28 March 2008 00:40
    To: cores@o...
    Subject: Re: [oc] Integrate I2C core into FPGA

    Guess was close, but off by a couple digits: PCA9564. I have the data
    sheet, and I would say I have an OK understanding of it's operation.
    Thank you very much for that explanation, it is very helpful. I've only
    been able to find one person that's even heard of the wishbone protocol
    and it ended there, he had only heard of it. But that explanation helps
    make sense out of the code. Even though it's not the same chip, the
    link helps too.


    ----- Original Message -----
    From: andrew mulcock<spam@m...>
    To:
    Date: Wed Mar 26 21:16:17 CET 2008
    Subject: [oc] Integrate I2C core into FPGA

    > Wishbone first.
    >
    > Wishbone is a 'computer bus' inside the FPGA with master and
    > peripherals (
    > slaves ).
    >
    > Think of an address bus and a data bus. On a PC the data would be
    > bi
    > directional, with tri state drivers on each peripheral.
    > As FPGA's don't support bi directional bus's the data bus is split
    > into two
    > one from master, one too master.
    > As FPGA's don't tend to support internal tri state bus's, then
    > 'and' gates
    > are used.
    > take the output of all the peripherals, and 'and' them together.
    > The 'trick' is to make certain the output of all but the
    > peripheral
    > you want is set at zero,
    > I guess you currently have a 'Philips' parallel to I2C chip,
    > PCF8584. which
    > is what you want to replace.
    > you might want to take a look here to get a handle on the
    chip
    > your
    > trying to replace.
    >
    >
    >
    http://www.ai.rug.nl/~pave/i2c/i2c_to_parallel_port_text.html#pcf8584
    > -----Original Message-----
    > From: cores-bounces at opencores.org [mailto:cores-bounces at
    > opencores.org] On
    > Behalf Of dslaman0877 at yahoo.com
    > Sent: 26 March 2008 18:12
    > To: cores at opencores.org
    > Subject: [oc] Integrate I2C core into FPGA
    > I'm currently working on a senior project (EE undergrad) where one
    > of
    > the requirements is to replace an existing I2C chip with a coded
    > version
    > of the I2C loaded directly onto the FPGA. I really want to use the
    > I2C
    > core from this site written by Richard Herveille, but I'm really
    > confused
    > about how the whole wishbone thing works.
    > The system the I2C is interfaced with is very simple. Overall, the
    > device is a camera. I have a KODAK board (imaging sensor) connected
    > to a board that contains all the electrical components (RAM, FPGA:
    > XCV300-4PQ240C in PQFP 240 pin package, USB DLP chip, I2C chip)
    > which connects to a computer via the USB port. Matlab owns the
    > whole process, there are 2 files written that write the KODAK
    > registers
    > and the reads them (for verification) over the I2C chip.
    > I've had to reverse engineer the project, I was given a prototype,
    > told
    > to figure it out by building the whole thing from the ground up,
    > and then
    > make the changes per requirements.
    > Currently, there is a statemachine in the VHDL code that evenutally
    > outputs received signals from the FPGA to the I2C chip. The only
    > pins
    > hooked up as outputs of the FPGA to inputs of the I2C chip are: A0,
    > A1,
    > WT', RD' CE', and RST'. D0-D7 (8-bit data line) is hooked up to the > I2C > as bi-directional data. Finally, I have the SCL and SDA lines > hooked up > to the Kodak board. > My idea was to redefine the outputs of the FPGA as internal signals > that > would map to the I2C core signals. I think that the clock > everything is > running off of needs to be mapped to the clock signal in the I2C > core as > well. I know I'm asking for a whole lot of help here, but I'm > really > running out of places to turn to. thanks > _______________________________________________ > http://www.opencores.org/mailman/listinfo/cores > No virus found in this incoming message. > Checked by AVG. > Version: 7.5.519 / Virus Database: 269.22.0/1343 - Release Date: > 25/03/2008 > 19:17 > No virus found in this outgoing message. > Checked by AVG. > Version: 7.5.519 / Virus Database: 269.22.0/1343 - Release Date: > 25/03/2008 > 19:17 > > > _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

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    [oc] Integrate I2C core into FPGADslaman0877

     
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