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Wishbone first.
Wishbone is a 'computer bus' inside the FPGA with master and peripherals (
slaves ).

Think of an address bus and a data bus. On a PC the data would be bi
directional, with tri state drivers on each peripheral.

As FPGA's don't support bi directional bus's the data bus is split into two
one from master, one too master.

As FPGA's don't tend to support internal tri state bus's, then 'and' gates
are used.
	take the output of all the peripherals, and 'and' them together.
	The 'trick' is to make certain the output of all but the peripheral
you want is set at zero, 

I guess you currently have a 'Philips' parallel to I2C chip, PCF8584. which
is what you want to replace.
	you might want to take a look here to get a handle on the chip your
trying to replace.

http://www.ai.rug.nl/~pave/i2c/i2c_to_parallel_port_text.html#pcf8584

-----Original Message-----
From: cores-bounces@o... [mailto:cores-bounces@o...] On
Behalf Of dslaman0877@y...
Sent: 26 March 2008 18:12
To: cores@o...
Subject: [oc] Integrate I2C core into FPGA

I'm currently working on a senior project (EE undergrad) where one of 
the requirements is to replace an existing I2C chip with a coded version 
of the I2C loaded directly onto the FPGA.  I really want to use the I2C 
core from this site written by Richard Herveille, but I'm really confused 
about how the whole wishbone thing works.  

The system the I2C is interfaced with is very simple.  Overall, the 
device is a camera.  I have a KODAK board (imaging sensor) connected 
to a board that contains all the electrical components (RAM, FPGA: 
XCV300-4PQ240C in PQFP 240 pin package, USB DLP chip, I2C chip) 
which connects to a computer via the USB port.  Matlab owns the 
whole process, there are 2 files written that write the KODAK registers 
and the reads them (for verification) over the I2C chip.  

I've had to reverse engineer the project, I was given a prototype, told 
to figure it out by building the whole thing from the ground up, and then 
make the changes per requirements.

Currently, there is a statemachine in the VHDL code that evenutally 
outputs received signals from the FPGA to the I2C chip.  The only pins 
hooked up as outputs of the FPGA to inputs of the I2C chip are: A0, A1, 
WT', RD' CE', and RST'.  D0-D7 (8-bit data line) is hooked up to the I2C 
as bi-directional data.  Finally, I have the SCL and SDA lines hooked up 
to the Kodak board.

My idea was to redefine the outputs of the FPGA as internal signals that 
would map to the I2C core signals.  I think that the clock everything is 
running off of needs to be mapped to the clock signal in the I2C core as 
well.  I know I'm asking for a whole lot of help here, but I'm really 
running out of places to turn to.  thanks

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