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Message
From: motilito at gmail.com<motilito@g...>
Date: Wed Jan 16 11:48:15 CET 2008
Subject: [oc] VHCG (Viterbi HDL Generator)
----- Original Message -----
From: wasay.rizwan at gmail.com<wasay.rizwan@g...>
To:
Date: Sat Jan 5 01:15:18 CET 2008
Subject: [oc] VHCG (Viterbi HDL Generator)
> Hi,
>
> I am looking at Viterbi hdl generator located here:
> http://www.opencores.org/projects.cgi/web/vhcg/overview
> The author has a brief help page here:
> http://viterbi-gen.sourceforge.net/
> How can you generate code rate: 1/2 k=7 hard decision decoder?
> There
> are no inputs for code rate or constraint length?
> Thanks,
> Wasay
>
>
Hi Wasay,
I used the VHCG to generate an IP with the same parameters (and I'm
almost sure with the same generator polynoms). I received a request
just a few days ago requesting the same help.
I copied the section about the generator parameters I used to generate
the core. I know that the generated core has some problems with the
test bench. I can also send you the core I generated and fixed if
required.
Good luck,
Moti
Short help for VHCG:
To generate the you can use the following parameters:
POLYS the generator polynoms in decimal format. you can see in the
core home page the first two values are the most common generators
used in decimal notation (91, 121) which are (133, 171) in octal format.
V = 1 the only supported value
B = 2 I required the core to be ready for new input metrics every
other clock cycle. As far as I could see this parameter works. It will set
the number of PE block actually implemented to be 2^(K-B-2). so the
size of the IP will very much depend on this parameter. the problem was
that for B>1 the generated testbench did not work. I do not remember
what exactly was wrong but it was very simple to fix.
OSR = 5 this means that the decoder will output 32 bits per traceback.
the original implementation of the IP requires that the traceback length
(TBL) will be a multiple of 2^OSR. after generating the IP you can take
a look at the " trabacknew2.v" file to find out more about the traceback
mechanism.
TBL = 64 You should note that the actual trace back length, as far as
I reffer to it, is 32 in this case. the IP will start the trace back every 32
bits starting from the last bit entering the traceback memory. the first
valid output bit shall be read after tracing back 32 bits. this means that
the first output bit in every traceback is the less reliable since only 32
bits where used in its traceback. Reducing OSR will improve the reliability
for the price of throughput.
RAW = 10 you can look in the generated code to see what this means.
You should note that the core does not support burst decoding. the
original implementation only works for continuous decoding. I also found
the traceback module to be very badly coded and made some major
changes to the file. The new traceback I wrote supports burst and does
not limit the traceback length.
If you wish to use the core with puncturing you might need the
traceback length to be more than 64 bits. I used something like 128.
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