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From: Iwan Kruger<14345609@s...>
Date: Sat Sep 29 11:31:59 CEST 2007
Subject: [oc] core cells
Hey

I'm using Designer of Libero to compile my program but when I compiled it I received an error that says "Error: [too_many_blocks]: Netlist contains too many blocks (12963) for the part (maximum = 3072)."

Thus I have to many core cells 12963 and it won't fit on to the FPGA ( APA075 ). Does any body have an idea how to decrease the core cells. ( or what may cause the cell count to increase dramatically )
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