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Message
From: jpcmisc at charter.net<jpcmisc@c...>
Date: Sat Sep 29 06:12:30 CEST 2007
Subject: [oc] i2c Slave Design Ideas
Hi all, I'm another newbie to I2C but learning fast (got the spec right
here!)
I'm currently looking at VHDL models for I2C slave designs (so far found
the one by Frank Buss) but ultimately I want to implement an I2C slave
in a custom CMOS mixed-signal IC.
My first thoughts were, that it seems like FPGA designers have the
luxury of "cheating" by using an external clock to register SDA and SCL.
This makes it not a 2-wire interface, technically, but sure makes it
easier. But since I cannot bring a high-speed clock onto my CMOS, I
need to do it using only the two I2C bus clocks (I assume that
commercial serial DAC makers do the same as they have no external
clock pin). From what I've read in previous email posts related to this
topic, it seems rational to try using both SDA and SCL as a clock (or
latch), depending on the need. I would just like for someone who's
already done this to confirm. My other guess is that chip makers
generate their own clock from an internal multivibrator ckt or something.
Does anyone have knowledge of a document, behavioral model, state
diagram, logic diagram, etc, that would help me with designing an I2C
slave (Fm or faster) that does not rely on an external clock?
Thanks all.
JP
----- Original Message -----
From: tkafafi at hotmail.com<tkafafi@h...>
To:
Date: Tue Sep 25 09:04:10 CEST 2007
Subject: [oc] i2c Slave Design Ideas
> Hi G-sus,
>
> I was faced with the same issue when I designed an i2c slave in the
> past. My decision was to use a higher speed clock to sample SCL and
> SDA. The rational was to allow digital debouncing of these signals
> since
> they have very slow transition times and are suceptible to noise
> induced
> glitches.
> If you do not think noise will be an issue in your environment you
> can
> the SCL as a clock. However, for detecting start and stop
> consitions, I
> recall that you need to use SDA as the clock and SCL as the data.
> Thanks
> ----- Original Message -----
> From: g-sus at gmx.li<g-sus at g...>
> To:
> Date: Sun Sep 2 15:52:10 CEST 2007
> Subject: [oc] i2c Slave Design Ideas
> > I am trying to implement an i2c slave and asking myself if i
> need a
> > clock or can use the incoming SCL as clock. i am a real vhdl
> newbie
> > and build a slave that triggers on the rising edge of the SCL
> line
> > for
> > reading the data ( except start and stop of course) and
> triggers on
> > the falling edge in order to set the statemachine (which
> determines
> > the next action) to the next state. Is this a correct and
> adequate
> > way
> > for building an i2c slave ?
> > thnx for your help ..
> >
> >
>
>
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