LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cores > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: Steve Wilson<stevew@k...>
    Date: Tue Sep 25 16:10:36 CEST 2007
    Subject: [oc] i2c Slave Design Ideas
    Top
    tkafafi@h... Wrote:
    >If you do not think noise will be an issue in your environment you can
    >the SCL as a clock. However, for detecting start and stop consitions, I
    >recall that you need to use SDA as the clock and SCL as the data.

    Let me confirm this point. The I2C specification requires the rejection of up
    to 50ns duration glitches. So use of a digital delay line that requires
    multiple clocks worth of stability is a must to get I2C to work.

    Don't forget that you can be driving up to 400pf worth of load - and the bus
    is going to have significant reflections.

    That digital filter seems to be a requirement in any significant (large)
    applications - and least anything not point to point.

    Steve Wilson

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.