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Message
From: Guy Hutchison<ghutchis@g...>
Date: Mon Sep 24 19:04:08 CEST 2007
Subject: [oc] Multi Valued Logic CPU Design Project
Short answer: No.The majority of projects on OpenCores target FPGAs, which can only build
binary-logic structures (although some interesting work was done using
genetic algorithms to create Xilinx bitstreams).
Doing multi-level logic requires access to a fab, a fistful of PhDs, a
boatload of analog designers, ability to do 4-5 trial tape-outs to get it to
work, and a decent-sized team of software folks to write up a new tool flow
for you.
MVL is a more optimal use of silicon resources, but for the people with
resources to tape out a chip, silicon is cheap. The biggest problem with
65nm is what to put in all that extra space you now have. Until we hit a
wall with process shrinks, I suspect this one will remain squarely in the
research category.
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