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Message
From: tkafafi at hotmail.com<tkafafi@h...>
Date: Tue Sep 25 09:04:10 CEST 2007
Subject: [oc] i2c Slave Design Ideas
Hi G-sus,I was faced with the same issue when I designed an i2c slave in the
past. My decision was to use a higher speed clock to sample SCL and
SDA. The rational was to allow digital debouncing of these signals since
they have very slow transition times and are suceptible to noise induced
glitches.
If you do not think noise will be an issue in your environment you can
the SCL as a clock. However, for detecting start and stop consitions, I
recall that you need to use SDA as the clock and SCL as the data.
Thanks
----- Original Message -----
From: g-sus at gmx.li<g-sus@g...>
To:
Date: Sun Sep 2 15:52:10 CEST 2007
Subject: [oc] i2c Slave Design Ideas
> I am trying to implement an i2c slave and asking myself if i need a
> clock or can use the incoming SCL as clock. i am a real vhdl newbie
> and build a slave that triggers on the rising edge of the SCL line
> for
> reading the data ( except start and stop of course) and triggers on
> the falling edge in order to set the statemachine (which determines
> the next action) to the next state. Is this a correct and adequate
> way
> for building an i2c slave ?
> thnx for your help ..
>
>
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