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Message
From: vax11780 at porky.vax-11.org<vax11780@p...>
Date: Tue Sep 25 04:15:13 CEST 2007
Subject: [oc] Multi Valued Logic CPU Design Project
On Sun, 23 Sep 2007, big one wrote:> Ordinary CPU use dual logic / binary logic 0 and 1.
> Multi Valued Logic use more than 2 values.
>
> According to Prof Moraga, Multi Valued Logic (MVL) CPU can run Operating System for Binary system using minimum as 0 and maximum as 1. The MVL can be manufactured using Silicon and Germanium (SiGe). Advantage of MVL:
> With 16 bit CPU, the flat memory address space is 43 Megabytes (16 x 16 x 16).
> Intel had released MVL based Flash RAM.
>
Most current flash memories store more than one bit per cell to reduce
die size.
> Is there any plan to create MVL CPU project on Opencores.org?
> Thank you.
>
Not to answer for everyone, but I doubt it.
Although it would be possible to rewrite the resolution rules in VHDL to
allow for more than the generally accepted 9, it would be a lot of work
and the result would be a simulation model which would never see
siliicon.
Clint
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