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Message
From: xinjianhong at 163.com<xinjianhong@1...>
Date: Thu Sep 13 06:48:31 CEST 2007
Subject: [oc] the errors of "tests.v" module?
hi,
At first,thanks for your AC'97 source code.
when I do the compile by Modelsim there is some errors with
the "tests.v" file,
I.E.
** Error: E:/work/AC97/ac97_ctrl/bench/verilog/tests.v(76): (vlog-
2155) Global declarations are illegal in Verilog 2001 syntax.
** Error: E:/work/AC97/ac97_ctrl/bench/verilog/tests.v(103):
Undefined variable: wb_busy.
** Error: E:/work/AC97/ac97_ctrl/bench/verilog/tests.v(104): Verilog
Compiler exiting
all others is OK,if u give me some suggestion i will be very happy.
thank you very much!
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