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From: galbo at gate.net<galbo@g...>
Date: Mon Sep 3 23:04:49 CEST 2007
Subject: [oc] I am having trouble editing a signal in a sub program IN VHDL
There are two places distinct blocks where reg_A is being written, this
is not permitted. A signal can only be driven (written) from one block
of code. That is, you have contention, there are 2 different circuits
trying to drive reg_A.

1) reg_A is written with "1111..." on rising clock in your unnamed
process
2) reg_A is written by your component ALU_test in the vlaggie
parameter, that is vlaggie is an OUTPUT. You can't do this.

BTW, assignment to a SIGNAL uses the symbol "<=". Your code is
correct. The symbol ":=" is used to assign a value to a VARIABLE.

Regards,
Neal



----- Original Message -----
From: 14345609 at sun.ac.za<14345609@s...>
To:
Date: Wed Aug 29 21:19:14 CEST 2007
Subject: [oc] I am having trouble editing a signal in a sub program
IN VHDL

> I declared a signal called reg_A. I then want to edit the signal in
> another subprogram. I basically want reg_A to be one of my inputs
> to a
> sub program(ALU_test) edit reg_A in the subprogram and then I
want
> the output of my subprogram to change reg_A in the main program
> (test). When I tried to do this an error occurred ("Signal
> reg_A has
> multiple sources"). I am not sure what to do could some one
> please
> help me.
> library ieee;
> use ieee.std_logic_1164.all;
> entity test is
> port ( clk : in std_logic;
> choze : in std_logic_vector(3 downto 0);
> data_t : in std_logic_vector(7 downto 0);
> Outw : out std_logic_vector(7 downto 0));
> end entity test;
> architecture no1 of test is
> ------------------------------------------------------------
> component ALU_test is
> port ( clk : in std_logic;
> choose : in std_logic_vector(3 downto 0);
> vlaggieIN : in std_logic_vector(7 downto 0);
> vlaggie : out std_logic_vector(7 downto 0));
> end component ALU_test;
> ------------------------------------------------------------
> signal reg_A
> : std_logic_vector(7 downto 0);
> ------------------------------------------------------------
> begin
> process (clk)
> begin
> if rising_edge(clk) then
> reg_A <= "11111111";
> end if;--if rising_edge(clk) then
> end process;
> r1: ALU_toets4 port map (clk,choze,reg_A,reg_A);
>
> Outw <= reg_A;
>
> end architecture no1;
>
> ---------------------------------------------------------------------
> -----
> ========================================
> =================
>
> ---------------------------------------------------------------------
> -----
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_unsigned.all;
> entity ALU_test is
> port ( clk : in std_logic;
> choose : in std_logic_vector(3 downto 0);
> vlaggieIN : in std_logic_vector(7 downto 0);
> vlaggie : out std_logic_vector(7 downto 0));
> end entity ALU_test;
> architecture alu1 of ALU_test is
>
> begin
> process (clk)
> begin
> if rising_edge(clk) then
> case choose is
> -----------------------------------
> -- add
> -----------------------------------
> when "1000" =>
> vlaggie <= "10101011" +
> vlaggieIN;
> -----------------------------------
> -- sub
> ----------------------------------- > when "0100" => > vlaggie <= "10100100"; > ----------------------------------- > -- maal > ----------------------------------- > when "0010" => > vlaggie <= vlaggieIN; > ----------------------------------- > when others => > vlaggie <= "00000000"; > ----------------------------------- > end case;--case kies is > > end if;--if rising_edge(clk) then > end process; > end architecture alu1; > >