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Message
From: Mark McDougall<markm@v...>
Date: Wed Aug 1 03:21:31 CEST 2007
Subject: [oc] Help with choosing a FPGA
Günter Dannoritzer wrote:> That is interesting and I did not know that. So it is possible to run
> the I/O of an FPGA with the internal PLL based clock, which will allow
> to clock in data faster than the external applied clock?
Absolutely. An internal high-speed PLL is much more accurate than an
external oscillator with associated variances due to - well, the physics
of it all. That's why you clock PCIe cores running at Gbps for example,
with 250MHz oscillators...
Regards,
--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
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