|
Message
From: Günter Dannoritzer<dannoritzer@w...>
Date: Tue Jul 31 10:53:51 CEST 2007
Subject: [oc] Help with choosing a FPGA
Mark McDougall wrote:
> a2e@i... wrote:
>
>> My fist question is
>> that if the onboard osc of the dev board is 50 MHz will that have any
>> bearing on the maximum frequency I can clock in at?
>
> No, FPGAs have internal PPLs that can synthesize a whole range of
> frequencies from an external clock input. One caveat - a quick experiment
> with the Quartus II megawizard reveals that you can't produce _exactly_
> 48MHz from a 50MHz clock - at least on Cyclone II - the dividers and
> multipliers don't pan out. Might be safer to use 24MHz in your case...
That is interesting and I did not know that. So it is possible to run
the I/O of an FPGA with the internal PLL based clock, which will allow
to clock in data faster than the external applied clock?
Cheers,
Guenter
|
 |
Browse
