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From: Stephen Warren<s-t-opencores@w...>
Date: Tue Jun 26 06:32:28 CEST 2007
Subject: [oc] Problem with T51 core & Xilinx ISE
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x-opencores.org@a... wrote:
> Hi,
>
> I'm trying to synthesize the T51 core (T8052) with Xilinx ISE on a
> Spartan 3-1000. The problem is that the synthesis takes (literally)
> hours. I had to stop it after two hours, didn't even get to the place
> & route stage.
>
> Is this normal? What I noticed is that the IRAMs are synthesized as
> Distributed RAM, not Block RAM, probably because the read address is
> not registered. Is that the reason for the long run time?

I don't have any experience with the T51 core, but I also suffered from
extreme synthesis times on the wb_z80 core. When I came back to it
later, and replaced the RAM with an explicit Xilinx BRAM instantiation,
everything was much quicker. I guess re-writing the RAM inference code
to register the output might have had the same effect, but I didn't try
that.

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