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Message
From: D R<heedaf@e...>
Date: Mon Mar 26 05:11:18 CEST 2007
Subject: [oc] Simulator 29 error
I've got a core in vhdl that I've placed in a schematic. It has "wb_adr_i : in unsigned(2 downto 0); " for one of the pins and I have a marker connected to the bin via the schematic. When I try and simulate I'm getting the following errorERROR:Simulator:29 - at 0 ns : in I2C_Test(BEHAVIORAL), file (null): Default port map for entity Tri_State_Added to component Tri_State_Added connects std_logic_vector type local port wb_adr_i of the component to UNSIGNED type port of the entity.I believe the problem is that wb_adr_i is "unsigned" and the schematic pin connection is being treated as "std_logic_vector". Does anyone have any idea what the solution is?Thanks,DR_______________________________________________
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