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From: Karim Aliopencores@g...>
Date: Sat Mar 24 02:58:20 CET 2007
Subject: [oc] Using Wishbone bus in Xilinx EDK
Hi,

I am a beginner developer using XPS with one of the Xilinx Virtex 2
Pro FPGA. The board came with a baseline defined by the manufacturer,
and it uses the Xilinx EDK (Xilinx Platform Studio).

I'm wondering how would I use these open cores that have been
developed with the Wishbone bus in mind. The Xilinx EDK only has the
IBM CoreConnect busses for use it seems.

I am currently trying to use the UART 16550 core on this site, and I
don't know how to access it through the software in my projects.

Any help is appreciated

Karim

Follow up	Author
[oc] Using Wishbone bus in Xilinx EDK	Mikhail Matusov